SalaryPeak

AI Chip Architecture Engineer – Hardware/Software Co-Design

CANAAN CREATIVE GLOBAL PTE. LTD.
Singapore Posted May 15, 2026

Salary Range

SGD 72,000 - SGD 120,000 /year

SGD 6,000 - SGD 10,000/month

Skills Required

Technology ArchitectureFlash MemoryElectric PowerHardware EngineeringTilingNOCLow LatencyAI acceleratorTransformerDistributed AlgorithmsDataflowoperator interfacesHardware DevelopmentScheduling

Job Description

Company Overview
Established in 2013, (Nasdaq: CAN) leads in high-performance ASIC chips, focusing on blockchain and AI. As the world’s first blockchain stock company, Canaan drives innovation in ASIC computing chips, AI chips, and devices.

Job Summary

Define and evaluate architectures for next-generation AI inference chips, focusing on Transformer and LLM workloads. Collaborate across teams to deliver optimized hardware-software co-design solutions and contribute innovative ideas to advance AI accelerator technology.

Responsibilities

  • Define and evaluate architectural features for next-generation AI inference chips to optimize performance and efficiency.
  • Analyze Transformer and LLM workloads to identify bottlenecks in performance, power, area, memory, and latency.
  • Explore and design AI accelerator architectures and microarchitectures, including compute arrays, memory hierarchy, NoC, DMA, scheduling, and dataflow.
  • Develop hardware-software co-design strategies for LLM inference, including operator mapping, tiling, memory planning, and compiler-guided optimization.
  • Collaborate with algorithm, compiler, RTL, verification, and software teams to deliver implementable architectural solutions.
  • Propose novel architecture ideas and contribute to patents and technical documentation.

Preferred competencies and qualifications

  • Bachelor’s degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
  • Strong knowledge of computer architecture, AI accelerators, memory hierarchy, interconnect, and performance analysis.
  • Familiarity with Transformer and LLM architecture components such as attention, FFN, quantization, KV cache, prefill, and decoding.
  • Experience with compiler frameworks or kernel optimization tools like MLIR, LLVM, TVM, XLA, or Triton.
  • Familiarity with hardware description languages such as Verilog, SystemVerilog, VHDL, or Chisel.
  • Strong analytical, communication, collaboration, and learning skills.
  • Fresh graduates with strong fundamentals and relevant project experience are encouraged to apply.